Complex electrical devices, which may be die, packaged ICs, or embedded cores within die or ICs, require test interfaces to allow testing of the device's hardware design. Further, these complex devices require debug interfaces to allow debugging of the devices hardware and software designs. These device test and debug interfaces require using some of the device's I/O terminals. For example, IEEE 1149.1 JTAG based test and debug of devices require dedicating four or five of a device's I/O terminals for use as a test and debug interface. Allocating device I/O terminals for test and debug interfaces eliminates those I/O terminals from being used as functional terminals.
Today very complex devices are being placed in smaller and smaller packages to allow more devices to be placed on tiny substrates, such as the miniature substrates used in cell phones. Small device packages typically have a reduced number of device I/O terminals, which creates competition between device terminals used for functionality and device terminals used for test and debug.
As a result of this competition for device terminal use, newer device test interfaces, such as the recently initiated IEEE P1149.7 standard, are being developed to reduce the number of device terminals required for test. While the IEEE P1149.7 standard provides a two terminal device test interface, even that smaller test interface will not offset future competition for functional and test/debug use of device terminals as package sizes continue to decrease. Ideally, and according to the present disclosure, device test and debug should be done without requiring dedicated use of any device terminals.
FIG. 1A illustrates an example of external test equipment 102, referred to hereafter as Tester, being coupled to the power 103, ground 105, and test terminals 106 of a device 104. Internal to the device 104, functional circuitry 108 and test circuitry 110 exists. The functional circuitry is coupled to functional terminals 112 and provides the functionality of the device. The test circuitry is coupled to test terminals 106 and provides the testing features of the device. Inside the device, the test circuitry interfaces to the functional circuitry to allow the functional circuitry to be tested.
Device test techniques include but are limited to; (1) internal scan testing whereby functional registers are converted into scan registers to allow shifting test patterns in and out of the device to test the combination circuitry of the function circuitry, (2) JTAG boundary scan testing whereby scan cells at the device boundary are used to test the device, (3) built in self testing (BIST) whereby internal test pattern generators and test pattern compactors are enabled to test combinational logic of the function circuitry, (4) built in test (BIT) whereby test code stored in non-volatile memory of the device is enabled to test the device, and (5) functional testing whereby a test code is uploaded into a memory of the device and executed to test the functionality of the device.
The Tester to device interface model shown in FIG. 1A is widely used today. This model uses dedicated device test terminals 106 which allows a device to be tested in a factory (manufacturing) or field (application) environment. Typically today, the Tester is interfaced to the device test circuitry using a dedicated IEEE standard 1149.1 (JTAG) test interface. However, other types of dedicated device test interfaces exists, such as but not limited to the IEEE standard 1149.4 test interface and the developing IEEE standard 1149.7 test interface bus. As long as the device has enough terminals, dedicated test signals can be used. However, in some cases (i.e. reduced pin count ICs) a device may not have enough terminals for both functional and test signals. In this case, dedicated device test terminals may not be available and device testing must be achieved by sharing terminals between functional and test use. Having to share device terminals for functional and test use eliminates the advantage of using the above mentioned IEEE standard test interfaces.
FIG. 1B illustrates an example of a wafer tester 114 contacting a die 116 on a wafer 128 for testing. The contact bus 126 between the tester and die includes; power contact signals 118-120 for powering up the die, test contact signals 122 for sending test inputs to and receiving test outputs from the die, and ground contact signals 124. The test contact signals 122 may be dedicated test pads of the die as mentioned in FIG. 1A, or functional pads that during test are converted into test pads (i.e. shared pads), or a mixture of dedicated and shared pads.
To reduce test time, and therefore test cost, it is advantageous to contact and simultaneously test as many die on a wafer as possible. This requires that the tester has a number of contact busses 126 equal to the number of die to be contacted and simultaneously tested. The cost of a tester grows as the number of contact signals in the contact bus 126 grow. In the industry today low cost wafer testers are being used to test multiple die on wafer. Reducing the number of contact signals in the contact bus 126 is one of the key ways to reduce the cost of a tester. Since the number of power 118-120 and ground 124 contact signals between a tester and die typically cannot be reduced due to the power a die consumes during test, the test input and output contact signals 122 are the ones usually targeted for reduction. The reduction of test input and output signals 122 is achieved by increasing the capability of the test circuitry 106 within the die 116.
FIG. 1C illustrates an example of an IC tester 130 contacting an IC 132 on a test fixture 134 for testing using a contact bus 136. For the sake of simplicity it is assumed that the IC tester 130 is the same as the wafer tester 114, the IC 130 is a packaged die 116, and the IC test contact bus 136 is the same as the die contact bus 126 of FIG. 1B. Also the test contact signals 122 may be dedicated, shared, or a mixture of dedicated and shared signals.
For the same reasons mentioned in regard to FIG. 1B, it is advantageous, cost-wise, to contact and simultaneously test as many ICs on the fixture as possible, which requires a number of contact busses 136 equal to the number of ICs to be contacted and simultaneously tested. Also, for the reasons mentioned in regard to FIG. 1B, it is advantageous to use low cost testers to test the ICs on the fixture, which requires reducing the number of test contacts 122 between the tester and ICs.
FIG. 1D illustrates the die on wafer testing of FIG. 1B as it would occur in a burn in chamber 138 whose temperature is controlled by a burn in temperature controller 140.
FIG. 1E illustrates the IC in fixture testing of FIG. 1C as it would occur in a burn in chamber 142 whose temperature is controlled by a burn in temperature controller 144.
FIG. 1F illustrates an example of external debug equipment 150, referred to hereafter as Debugger, being coupled to the debug the terminals 156 of a device 152. Internal to the device 152, functional circuitry 108 and debug circuitry 154 exist. The functional circuitry is coupled to functional terminals 112 and provides the functionality of the device. The debug circuitry is coupled to debug terminals 156 and provides the debugging features of the device. Inside the device, the debug circuitry interfaces to the functional circuitry to allow the operation of the functional circuitry and the controlling software to be debugged.
Device debug techniques include but are not limited to the following type of operations. (1) Uploading software into the memory of the functional circuitry for execution during software development and debug. (2) Loading breakpoint patterns into debug registers/memories coupled, via comparator circuits, to the address and/or data busses of the functional circuitry to allow triggering a debug operation to occur in response to a match between the breakpoint patterns and patterns occurring on the address and/or data busses during functional operation of the device. (3) Halting the functional operation of the device in response to the occurrence of a breakpoint trigger to allow upload and/or download of functional software or debug information. (4) Performing a trace operation whereby functionally occurring address and/or data bus patterns are stored in a trace buffer memory in the debug circuitry in response to a breakpoint trigger. (5) Performing a trace buffer output operation whereby functional address and/or data bus patterns stored in the trace buffer memory are output from the device to the debugger in response to a debug command input or in response to the occurrence of a breakpoint trigger. (6) Performing real-time trace output of address and/or data patterns occurring in the device during normal device operation.
The debugger to device interface model shown in FIG. 1F is widely used today. The key advantage of this model is the use of dedicated device debug terminals which allow debug operations to occur while the device is in functional operation mode. Typically today, the debugger is interfaced to the device debug circuitry using a JTAG interface. However, other types of debugger to device interfaces exists, such as ARM's single wire debug (SWD) interface bus, Debug Innovation's J-Link (JLINK) interface bus, and the developing IEEE 1149.7 test/debug interface bus. Regardless of the type of debug interface used, all state of the art device debugging done today make use of dedicated debug terminals on the device to allow debug to occur coincident with the functional operation of the device.
The present disclosure, as will be described in detail below, allows device testing and/or debugging to occur without requiring use of any device terminals, other than the device power and ground terminals. Therefore the present disclosure advantageously enables; (1) all device terminals to be used for functionality to support reduced pin count IC packaging, (2) use of IEEE test standards without requiring dedicated test terminals on the device, and (3) lower cost testers since the contact bus between a tester and a device only includes the device's power and ground signals.